The present invention relates to integrated circuit memories and more specifically to a system and method for refreshing a dynamic random access memory (DRAM).
Recently, there is much interest in using DRAMs in a variety of hand-held portable devices such as mobile communication devices, game units and personal digital assistants, mainly because of the greater amount of integration density that can be achieved over other types of rewriteable integrated circuit memory such as static random access memory (SRAM). In addition, DRAMs generally provide faster access time than some non-volatile types of rewriteable memory such as flash memory, and can be written at considerably lower voltages than those required for flash memory.
However, owing to their compact design of having a single transistor and a storage capacitor per storage cell, DRAMs require refreshing in order to prevent the data stored in the storage cells from disappearing as a leakage current from the storage capacitor of each storage cell. During refresh, a data bit signal is read from each storage cell, then amplified to full logic levels and is then restored to the storage cell.
Different storage cells of a DRAM can tolerate being refreshed at different rates. Variations in the manufacturing process within tolerances can result in the storage cells of particular portions of the DRAM having greater or less leakage current. Some storage cells of the DRAM, because of their marginal characteristics, may require refreshing at the conventional rate of once every 64 msec. However, other storage cells of the DRAM may require refreshing only at much less frequent intervals, for example, 128 msec, 256 msec, 512 msec, or at intervals extending into seconds. Conventionally, all storage cells of a DRAM are refreshed at the same refresh rate. Because of this, it is apparent that the refresh rate must be set at the point required by the weakest storage cell of the DRAM.
While conventional refreshing at a single rate is acceptable for DRAMs installed in systems having much available power, such is not desirable for portable devices, due to the need to extend battery charge by conserving power. This is especially important for extending the standby time of portable devices such that data can be maintained in DRAM of the portable device for a desirably long time.
Standard DRAMs of 256 K capacity draw refresh currents in the range of 500 μA. This is based upon refreshing the entire DRAM at the conventional refresh interval of 64 msec. Such refresh currents are unacceptably high for a portable device, since they are always present during both an active mode of the DRAM and a sleep mode when provided in the DRAM, regardless of whether a user is actively using the portable device or not. Conventionally, lower refresh currents are obtained only when the DRAM or portions thereof are switched off.
As used herein in connection with a DRAM and particular portions thereof, the term “active mode” means the operational state in which data can be stored to and accessed from the DRAM, or the particular portions thereof.
As used herein in connection with a DRAM and particular portions thereof, the term “sleep mode” means the operational state in which data remains stored in a DRAM or particular portions thereof subject to being refreshed, but in which mode data cannot be stored to and accessed from the DRAM or the particular portions thereof.
As used herein in connection with a DRAM and particular portions thereof, the term “switched off” means the state in which power that is input to the DRAM or particular portions thereof, is either removed from the DRAM or set to a level that is insufficient for the DRAM to reliably store data.
FIG. 1 illustrates a DRAM 10 in which conventional refreshing is performed. As illustrated in FIG. 1, the DRAM 10 includes four segments 12, 14, 16, and 18, a row decoder/driver unit 20 for activating wordlines of each segment of the DRAM, and a refresh controller 22 having self-refresh logic and a counter for controlling the addresses and timing at which portions of the DRAM are refreshed.
During refreshing, the refresh controller 22 causes row decoder/driver unit 20 to activate a wordline of a segment 12, 14, 16, or 18, at which time signals representing data bits stored in storage cells accessed by the particular wordline are read out, amplified to full logic levels and then restored to the storage cells. Thereafter, the refresh controller 22 does the same for the next wordline in sequence, and then the next one thereafter, until all of the storage cells accessed by all of the wordlines have been refreshed for all of the segments. In this conventional arrangement, the storage cells of all of the wordlines are refreshed at the same refresh rate, i.e., once every 64 msec.
Because different portions of a DRAM require more or less frequent refreshing, it would be desirable to provide a way of distinguishing between respective portions of a DRAM in which one portion requires a first refresh rate and another portion which can be refreshed at a rate which is lower than the first refresh rate.
Further, it would be desirable to refresh the respective portions of a DRAM so distinguished from each other at different rates.